//Copyright (C)2014-2023 GOWIN Semiconductor Corporation.
//All rights reserved.
//File Title: Timing Constraints file
//GOWIN Version: 1.9.9 Beta-4 Education
//Created Time: 2023-10-29 21:23:40
create_clock -name sys_clk -period 37.037 -waveform {0 18.518} [get_ports {sys_clk}]
create_clock -name clk1m -period 1000 -waveform {0 500} [get_nets {mdc_d}]
create_clock -name clk25m -period 40 -waveform {0 20} [get_nets {clk_25m}]
create_clock -name eth_clk -period 20 -waveform {0 10} [get_ports {eth_clk}]
set_false_path -from [get_clocks {clk25m}] -to [get_clocks {sys_clk}] 
